//-----------------------------------------------------------------------------
// Title         : ステートマシン
// Project       : 例題
//-----------------------------------------------------------------------------
// File          : state_machine.v
// Author        : hoge@foo
// Created       : 03.12.2005
// Last modified : 03.12.2005
//-----------------------------------------------------------------------------
// Description :
// 
//-----------------------------------------------------------------------------
// Copyright (c) 2005 by Ryusai This model is the confidential and
// proprietary property of Ryusai and the possession or use of this
// file requires a written license from Ryusai.
//-----------------------------------------------------------------------------
// Modification history :
// 03.12.2005 : created
//-----------------------------------------------------------------------------

module state_machine(/*AUTOARG*/
                     // Outputs
                     PReady, oen, wen,
                     // Inputs
                     clk, reset, PStrobe, PRW, cen
                     );
   input clk;
   input reset;
   input PStrobe;
   input PRW;
   input cen;
   output PReady;
   output oen;
   output wen;

   reg    oen;
   reg    wen;
   reg    PReady;
   
   // ステートの定義
   reg [1:0] state;
   reg [1:0] next_state;
   
   parameter IDLE=2'b00;
   parameter READ=2'b01;
   parameter WRIT=2'b10;

   always @(posedge clk) state <= next_state;
      
   always @(posedge clk) begin
      if (!reset) 
        next_state <= IDLE;
      else if (cen)
        next_state <= IDLE; 
      else begin
         case (state)
           IDLE:begin
              if (PStrobe && PRW)
                next_state <= READ;
	      else if (PStrobe && !PRW)
		next_state <= WRIT;
	   end
	   
           READ: begin
              next_state <= IDLE;
	   end
	   
           WRIT: begin
              next_state <= IDLE;
	   end
	   
           default:
	     next_state <= IDLE;
	   
         endcase // case(state)
      end // else: !if(cen)
   end // always @ (posedge clk)

   task output_vec;
      input [2:0] vec;
      {oen, wen, PReady} = vec;
   endtask
 
   always @(state)
     case (state)
       IDLE: output_vec(3'b110);
       READ: output_vec(3'b011);
       WRIT: output_vec(3'b101);
       default: output_vec(3'b110);
     endcase // case(state)
endmodule // state_machine